This is a preparation for AVX512-FP16, where the broadcast size is not
just 32/64 bit depending solely on EVEX.W, but can also be 16 bit (with
EVEX.W=0). The broadcast size therefore needs two bits, but the evex
field only had one free bit left. Store broadcast size with the segment
for now. (This is not a good fit and is likely to change at some point.)
- 3DNow! instructions have a trailing immediate byte which indicates the
opcode. Decoding this with the existing table structure requires more
effort (in particular, a new lookup table after decoding ModRM would
be required). Given that AMD even removed 3DNow! over 10 years ago, it
appears unlikely that this will ever be fully supported. Adding the
RMI-encoded pseudo-instruction "3DNOW" just to support that opcode.
- FEMMS is a legacy 3DNow! instruction.
- EXTRQ/INSERTQ are instructions with an "unusual" encoding and
operation mode. This is another instance of 16-bit immediates.
- SVM (AMD's variant of VMX) and SNP instructions are AMD-only.
The formatter now includes the following information:
- Segment overrides
- Address-size overrides
- REP/REPNZ prefixes
- LOCK prefix
- High-byte registers (determined using presence of REX prefix)
