From f565f09f9dc1e87e7c19de6ab103a6f3b2b062d4 Mon Sep 17 00:00:00 2001 From: Alexis Engelke Date: Sun, 27 Nov 2022 17:01:06 +0100 Subject: [PATCH] instrs: Clearly separate vector and GP opsize Now, an instruction cannot refer to the GP operand size and the vector operand size at the same time. This isn't necessary, all necessary distinguishing could also be achieved manually using W0/W1/66 selectors. --- decode-test.c | 3 +-- encode-test.inc | 1 + instrs.txt | 36 ++++++++++++++++++------------------ parseinstrs.py | 3 +++ 4 files changed, 23 insertions(+), 20 deletions(-) diff --git a/decode-test.c b/decode-test.c index 0817aea..0761286 100644 --- a/decode-test.c +++ b/decode-test.c @@ -547,8 +547,7 @@ main(int argc, char** argv) TEST("\xc4\xe3\xf9\x14\xc0\x00", "vpextrb eax, xmm0, 0x0"); TEST("\xc4\xe3\x79\x15\xc0\x00", "vpextrw eax, xmm0, 0x0"); TEST("\xc4\xe3\xf9\x15\xc0\x00", "vpextrw eax, xmm0, 0x0"); - TEST32("\xc4\xe1\x79\xc5\xc0\x00", "vpextrw eax, xmm0, 0x0"); - TEST64("\xc4\xe1\x79\xc5\xc0\x00", "vpextrw rax, xmm0, 0x0"); + TEST("\xc4\xe1\x79\xc5\xc0\x00", "vpextrw eax, xmm0, 0x0"); TEST("\xc4\xe3\x79\x16\xc0\x00", "vpextrd eax, xmm0, 0x0"); TEST32("\xc4\xe3\xf9\x16\xc0\x00", "vpextrd eax, xmm0, 0x0"); TEST64("\xc4\xe3\xf9\x16\xc0\x00", "vpextrq rax, xmm0, 0x0"); diff --git a/encode-test.inc b/encode-test.inc index 2b86231..f9c62ac 100644 --- a/encode-test.inc +++ b/encode-test.inc @@ -261,6 +261,7 @@ TEST("\xc5\xf1\x71\xd7\x02", VPSRLW128rri, 0, FE_XMM1, FE_XMM7, 0x2); TEST("\xc5\xf5\x71\xd7\x02", VPSRLW256rri, 0, FE_XMM1, FE_XMM7, 0x2); TEST("\xc4\xc3\xfd\x00\xc9\x12", VPERMQ256rri, 0, FE_XMM1, FE_XMM9, 0x12); TEST("\xc4\xe3\xfd\x01\xcf\x12", VPERMPD256rri, 0, FE_XMM1, FE_XMM7, 0x12); +TEST("\xc5\xf9\xc5\xc0\x00", VPEXTRWrri, 0, FE_AX, FE_XMM0, 0x0); // Test RVMR encoding TEST("\xc4\xe3\x71\x4a\xc2\x30", VBLENDVPS128rrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2, FE_XMM3); diff --git a/instrs.txt b/instrs.txt index 7b455a4..66e3ff5 100644 --- a/instrs.txt +++ b/instrs.txt @@ -631,8 +631,8 @@ NP.0f2e RM Vss Wss - - SSE_UCOMISS F=SSE EFL=0--0m0 66.0f2e RM Vsd Wsd - - SSE_UCOMISD F=SSE2 EFL=0--0m0mm NP.0f2f RM Vss Wss - - SSE_COMISS F=SSE EFL=0--0m0mm 66.0f2f RM Vsd Wsd - - SSE_COMISD F=SSE2 EFL=0--0m0mm -NP.0f50/r RM Gy Ups - - SSE_MOVMSKPS D64 F=SSE -66.0f50/r RM Gy Upd - - SSE_MOVMSKPD D64 F=SSE2 +NP.0f50/r RM Gy Udq - - SSE_MOVMSKPS D64 F=SSE +66.0f50/r RM Gy Udq - - SSE_MOVMSKPD D64 F=SSE2 NP.0f51 RM Vps Wps - - SSE_SQRTPS F=SSE 66.0f51 RM Vpd Wpd - - SSE_SQRTPD F=SSE2 F3.0f51 RM Vss Wss - - SSE_SQRTSS F=SSE @@ -694,8 +694,8 @@ F2.0f5f RM Vsd Wsd - - SSE_MAXSD F=SSE2 66.0f6b RM Vx Wx - - SSE_PACKSSDW F=SSE2 66.0f6c RM Vx Wx - - SSE_PUNPCKLQDQ F=SSE2 66.0f6d RM Vx Wx - - SSE_PUNPCKHQDQ F=SSE2 -66.W0.0f6e RM Vx Ey - - SSE_MOVD_G2X F=SSE2 ENC_NOSZ -66.W1.0f6e RM Vx Ey - - SSE_MOVQ_G2X F=SSE2 ENC_NOSZ +66.W0.0f6e RM Vx Ed - - SSE_MOVD_G2X F=SSE2 ENC_NOSZ +66.W1.0f6e RM Vx Eq - - SSE_MOVQ_G2X F=SSE2 ENC_NOSZ 66.0f6f RM Vx Wx - - SSE_MOVDQA F=SSE2 F3.0f6f RM Vx Wx - - SSE_MOVDQU F=SSE2 66.0f70 RMI Vx Wx Ib - SSE_PSHUFD F=SSE2 @@ -752,7 +752,7 @@ F2.0fd0 RM Vpd Wpd - - SSE_ADDSUBPS F=SSE3 66.0fd5 RM Vx Wx - - SSE_PMULLW F=SSE2 # This is tricky, MOVQ to mem writes 64 bits, MOVQ to reg writes 128 bits 66.0fd6 MR Wq Vq - - SSE_MOVQ F=SSE2 -66.0fd7/r RM Gy Ux - - SSE_PMOVMSKB D64 F=SSE2 +66.0fd7/r RM Gy Udq - - SSE_PMOVMSKB D64 F=SSE2 66.0fd8 RM Vx Wx - - SSE_PSUBUSB F=SSE2 66.0fd9 RM Vx Wx - - SSE_PSUBUSW F=SSE2 66.0fda RM Vx Wx - - SSE_PMINUB F=SSE2 @@ -854,16 +854,16 @@ NP.0f38f9/m MR My Gy - - MOVDIRI F=MOVDIRI 66.0f3a0e RMI Vx Wx Ib - SSE_PBLENDW F=SSE41 66.0f3a0f RMI Vx Wx Ib - SSE_PALIGNR F=SSSE3 66.0f3a14/m MRI Mb Vx Ib - SSE_PEXTRB F=SSE41 -66.0f3a14/r MRI Ry Vx Ib - SSE_PEXTRB F=SSE41 ENC_NOSZ +66.0f3a14/r MRI Rd Vx Ib - SSE_PEXTRB F=SSE41 ENC_NOSZ 66.0f3a15/m MRI Mw Vx Ib - SSE_PEXTRW F=SSE41 -66.0f3a15/r MRI Ry Vx Ib - SSE_PEXTRW F=SSE41 ENC_NOSZ -66.W0.0f3a16 MRI Ey Vx Ib - SSE_PEXTRD F=SSE41 ENC_NOSZ -66.W1.0f3a16 MRI Ey Vx Ib - SSE_PEXTRQ F=SSE41 ENC_NOSZ +66.0f3a15/r MRI Rd Vx Ib - SSE_PEXTRW F=SSE41 ENC_NOSZ +66.W0.0f3a16 MRI Ed Vx Ib - SSE_PEXTRD F=SSE41 ENC_NOSZ +66.W1.0f3a16 MRI Eq Vx Ib - SSE_PEXTRQ F=SSE41 ENC_NOSZ 66.0f3a17 MRI Ed Vx Ib - SSE_EXTRACTPS F=SSE41 66.0f3a20 RMI Vx Eb Ib - SSE_PINSRB F=SSE41 66.0f3a21 RMI Vps Wss Ib - SSE_INSERTPS F=SSE41 -66.W0.0f3a22 RMI Vx Ey Ib - SSE_PINSRD F=SSE41 ENC_NOSZ -66.W1.0f3a22 RMI Vx Ey Ib - SSE_PINSRQ F=SSE41 ENC_NOSZ +66.W0.0f3a22 RMI Vx Ed Ib - SSE_PINSRD F=SSE41 ENC_NOSZ +66.W1.0f3a22 RMI Vx Eq Ib - SSE_PINSRQ F=SSE41 ENC_NOSZ 66.0f3a40 RMI Vps Wps Ib - SSE_DPPS F=SSE41 66.0f3a41 RMI Vpd Wpd Ib - SSE_DPPD F=SSE41 66.0f3a42 RMI Vx Wx Ib - SSE_MPSADBW F=SSE41 @@ -938,8 +938,8 @@ VEX.NP.LIG.0f2e RM Vss Wss - - VUCOMISS F=AVX EFL=0--0m0 VEX.66.LIG.0f2e RM Vsd Wsd - - VUCOMISD F=AVX EFL=0--0m0mm VEX.NP.LIG.0f2f RM Vss Wss - - VCOMISS F=AVX EFL=0--0m0mm VEX.66.LIG.0f2f RM Vsd Wsd - - VCOMISD F=AVX EFL=0--0m0mm -VEX.NP.0f50/r RM Gy Ups - - VMOVMSKPS D64 F=AVX -VEX.66.0f50/r RM Gy Upd - - VMOVMSKPD D64 F=AVX +VEX.NP.0f50/r RM Gd Ups - - VMOVMSKPS F=AVX +VEX.66.0f50/r RM Gd Upd - - VMOVMSKPD F=AVX VEX.NP.0f51 RM Vps Wps - - VSQRTPS F=AVX VEX.66.0f51 RM Vpd Wpd - - VSQRTPD F=AVX VEX.F3.LIG.0f51 RVM Vdq Hdq Wss - VSQRTSS F=AVX @@ -1043,7 +1043,7 @@ VEX.66.0fc2 RVMI Vx Hx Wx Ib VCMPPD F=AVX VEX.F3.LIG.0fc2 RVMI Vx Hx Wss Ib VCMPSS F=AVX VEX.F2.LIG.0fc2 RVMI Vx Hx Wsd Ib VCMPSD F=AVX VEX.66.WIG.L0.0fc4 RVMI Vx Hx Ew Ib VPINSRW F=AVX ENC_NOSZ -VEX.66.WIG.L0.0fc5/r RMI Gy Ux Ib - VPEXTRW D64 F=AVX ENC_NOSZ +VEX.66.WIG.L0.0fc5/r RMI Gd Ux Ib - VPEXTRW F=AVX ENC_NOSZ VEX.NP.0fc6 RVMI Vx Hx Wx Ib VSHUFPS F=AVX VEX.66.0fc6 RVMI Vx Hx Wx Ib VSHUFPD F=AVX VEX.NP.0fd0 RVM Vx Hx Wx - VADDSUBPS F=AVX @@ -1054,7 +1054,7 @@ VEX.66.0fd3 RVM Vx Hx Wx - VPSRLQ F=AVX VEX.66.0fd4 RVM Vx Hx Wx - VPADDQ F=AVX VEX.66.0fd5 RVM Vx Hx Wx - VPMULLW F=AVX VEX.66.L0.0fd6 MR Wq Vq - - VMOVQ F=AVX -VEX.66.0fd7/r RM Gy Ux - - VPMOVMSKB D64 F=AVX +VEX.66.0fd7/r RM Gd Ux - - VPMOVMSKB F=AVX VEX.66.0fd8 RVM Vx Hx Wx - VPSUBUSB F=AVX VEX.66.0fd9 RVM Vx Hx Wx - VPSUBUSW F=AVX VEX.66.0fda RVM Vx Hx Wx - VPMINUB F=AVX @@ -1259,9 +1259,9 @@ VEX.66.WIG.L0.0f3a14/m MRI Mb Vx Ib - VPEXTRB F=AVX ENC_NOSZ VEX.66.WIG.L0.0f3a14/r MRI Rd Vx Ib - VPEXTRB F=AVX ENC_NOSZ VEX.66.WIG.L0.0f3a15/m MRI Mw Vx Ib - VPEXTRW F=AVX ENC_NOSZ VEX.66.WIG.L0.0f3a15/r MRI Rd Vx Ib - VPEXTRW F=AVX ENC_NOSZ -VEX.66.W0.L0.0f3a16 MRI Ey Vx Ib - VPEXTRD F=AVX ENC_NOSZ -VEX.66.W1.L0.0f3a16 MRI Ey Vx Ib - VPEXTRD I64 F=AVX ENC_NOSZ -VEX.66.W1.L0.0f3a16 MRI Ey Vx Ib - VPEXTRQ O64 F=AVX ENC_NOSZ +VEX.66.W0.L0.0f3a16 MRI Ed Vx Ib - VPEXTRD F=AVX ENC_NOSZ +VEX.66.W1.L0.0f3a16 MRI Ed Vx Ib - VPEXTRD I64 F=AVX ENC_NOSZ +VEX.66.W1.L0.0f3a16 MRI Eq Vx Ib - VPEXTRQ O64 F=AVX ENC_NOSZ VEX.66.L0.0f3a17 MRI Ed Vx Ib - VEXTRACTPS F=AVX ENC_NOSZ VEX.66.W0.L1.0f3a18 RVMI Vx Hx Wdq Ib VINSERTF128 F=AVX ENC_NOSZ VEX.66.W0.L1.0f3a19 MRI Wdq Vx Ib - VEXTRACTF128 F=AVX ENC_NOSZ diff --git a/parseinstrs.py b/parseinstrs.py index 247a463..918215e 100644 --- a/parseinstrs.py +++ b/parseinstrs.py @@ -227,6 +227,9 @@ class InstrDesc(NamedTuple): extraflags = {} opsz = set(self.OPKIND_SIZES[opkind.size] for opkind in self.operands) + # Operand size either refers to vectors or GP, but not both + if -2 in opsz and -3 in opsz: + raise Exception(f"conflicting gp vs. vec operand size in {self}") # Sort fixed sizes encodable in size_fix2 as second element. fixed = sorted((x for x in opsz if x >= 0), key=lambda x: 1 <= x <= 4)