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instrs: Specify segment register size

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This commit is contained in:
Alexis Engelke
2020-07-04 08:52:08 +02:00
parent 0da46cba98
commit dc668691d8
3 changed files with 6 additions and 6 deletions
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4
instrs.txt
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@@ -139,9 +139,9 @@
89 MR GP GP - - MOV 89 MR GP GP - - MOV
8a RM GP GP - - MOV SIZE_8 8a RM GP GP - - MOV SIZE_8
8b RM GP GP - - MOV 8b RM GP GP - - MOV
8c MR GP SREG - - MOV_S2G 8c MR GP16 SREG - - MOV_S2G
8d RM GP MEMZ - - LEA 8d RM GP MEMZ - - LEA
8e RM SREG GP - - MOV_G2S 8e RM SREG GP16 - - MOV_G2S
8f/0 M GP - - - POP DEF64 8f/0 M GP - - - POP DEF64
# Against frequent belief, only, XCHG (r/e)AX, (r)AX with 90 is NOP. # Against frequent belief, only, XCHG (r/e)AX, (r)AX with 90 is NOP.
# As a lacking REX.B cannot be specified here, this is hardcoded. # As a lacking REX.B cannot be specified here, this is hardcoded.

2
parseinstrs.py
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@@ -110,7 +110,7 @@ OPKINDS = {
"XMM64": OpKind(8, "XMM"), "XMM64": OpKind(8, "XMM"),
"XMM128": OpKind(16, "XMM"), "XMM128": OpKind(16, "XMM"),
"XMM256": OpKind(32, "XMM"), "XMM256": OpKind(32, "XMM"),
"SREG": OpKind(0, "SEG"), "SREG": OpKind(2, "SEG"),
"FPU": OpKind(10, "FPU"), "FPU": OpKind(10, "FPU"),
"MEM": OpKind(OpKind.SZ_OP, OpKind.K_MEM), "MEM": OpKind(OpKind.SZ_OP, OpKind.K_MEM),
"MEMV": OpKind(OpKind.SZ_VEC, OpKind.K_MEM), "MEMV": OpKind(OpKind.SZ_VEC, OpKind.K_MEM),

6
tests/test_decode.c
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@@ -86,9 +86,9 @@ main(int argc, char** argv)
TEST64("\x0f\x20\xd0", "[MOV_CR reg8:r0 reg0:r2]"); TEST64("\x0f\x20\xd0", "[MOV_CR reg8:r0 reg0:r2]");
TEST64("\x44\x0f\x20\x08", "UD"); TEST64("\x44\x0f\x20\x08", "UD");
TEST64("\x44\x0f\x21\x00", "UD"); TEST64("\x44\x0f\x21\x00", "UD");
TEST("\x8c\xc0", "[MOV_S2G reg4:r0 reg0:r0]"); TEST("\x8c\xc0", "[MOV_S2G reg2:r0 reg2:r0]");
TEST64("\x44\x8c\xc0", "[MOV_S2G reg4:r0 reg0:r0]"); TEST64("\x44\x8c\xc0", "[MOV_S2G reg2:r0 reg2:r0]");
TEST("\x8e\xc0", "[MOV_G2S reg0:r0 reg4:r0]"); TEST("\x8e\xc0", "[MOV_G2S reg2:r0 reg2:r0]");
TEST("\x8e\xc8", "UD"); // No mov cs, eax TEST("\x8e\xc8", "UD"); // No mov cs, eax
TEST("\xd8\xc1", "[FADD reg0:r0 reg0:r1]"); TEST("\xd8\xc1", "[FADD reg0:r0 reg0:r1]");
TEST64("\x41\xd8\xc1", "[FADD reg0:r0 reg0:r1]"); TEST64("\x41\xd8\xc1", "[FADD reg0:r0 reg0:r1]");