T0b1/fadec
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Unify instruction mnemonics [API break]

Browse Source 
It is a longer standing issue that some instructions like ADD, IMUL, and
SHL have multiple mnemonics for different encoding forms. This is a
relict from a time where such information was not stored in the
instruction decoding. This, however, is no longer the case and therefore
the extra mnemonics just increase the number of cases to be handled by
users.
This commit is contained in:
Alexis Engelke
2020-02-20 10:49:46 +01:00
parent 513a913feb
commit dc286b14f2
6 changed files with 167 additions and 167 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
tests/decode-enter.sh
View File

@@ -7,5 +7,5 @@ decode32 c8000001 [ENTER_4 imm4:0x10000]
decode64 c8000000 [ENTER_8 imm4:0x0]
decode64 c8000f00 [ENTER_8 imm4:0xf00]
decode64 c8000001 [ENTER_8 imm4:0x10000]
decode64 d3e0 [SHL_CL reg4:r0 reg1:r1]
decode64 0fa5d0 [SHLD_CL reg4:r0 reg4:r2 reg1:r1]
decode64 d3e0 [SHL reg4:r0 reg1:r1]
decode64 0fa5d0 [SHLD reg4:r0 reg4:r2 reg1:r1]

4
tests/decode-imul.sh
View File

@@ -1,2 +1,2 @@
decode 69C708010000 [IMUL3 reg4:r0 reg4:r7 imm4:0x108]
decode 6BC708 [IMUL3 reg4:r0 reg4:r7 imm4:0x8]
decode 69C708010000 [IMUL reg4:r0 reg4:r7 imm4:0x108]
decode 6BC708 [IMUL reg4:r0 reg4:r7 imm4:0x8]

18
tests/decode-ret.sh
View File

@@ -1,12 +1,12 @@
decode 66c3 [RET_2]
decode 66c20000 [RET_IMM_2 imm2:0x0]
decode 66c20d00 [RET_IMM_2 imm2:0xd]
decode 66c20dff [RET_IMM_2 imm2:0xff0d]
decode 66c20000 [RET_2 imm2:0x0]
decode 66c20d00 [RET_2 imm2:0xd]
decode 66c20dff [RET_2 imm2:0xff0d]
decode32 c3 [RET_4]
decode32 c20000 [RET_IMM_4 imm2:0x0]
decode32 c20d00 [RET_IMM_4 imm2:0xd]
decode32 c20dff [RET_IMM_4 imm2:0xff0d]
decode32 c20000 [RET_4 imm2:0x0]
decode32 c20d00 [RET_4 imm2:0xd]
decode32 c20dff [RET_4 imm2:0xff0d]
decode64 c3 [RET_8]
decode64 c20000 [RET_IMM_8 imm2:0x0]
decode64 c20d00 [RET_IMM_8 imm2:0xd]
decode64 c20dff [RET_IMM_8 imm2:0xff0d]
decode64 c20000 [RET_8 imm2:0x0]
decode64 c20d00 [RET_8 imm2:0xd]
decode64 c20dff [RET_8 imm2:0xff0d]

8
tests/decode-sse-movq.sh
View File

@@ -1,7 +1,7 @@
decode f30f7e5c2408 [SSE_MOVQ_X2X reg8:r3 mem8:r4+0x8]
decode c5f96ec8 [VMOVD_G2X reg4:r1 reg4:r0]
decode64 c4e1f96ec8 [VMOVQ_G2X reg8:r1 reg8:r0]
decode32 c4e1f96ec8 [VMOVD_G2X reg4:r1 reg4:r0]
decode f30f7e5c2408 [SSE_MOVQ reg8:r3 mem8:r4+0x8]
decode c5f96ec8 [VMOVD reg4:r1 reg4:r0]
decode64 c4e1f96ec8 [VMOVQ reg8:r1 reg8:r0]
decode32 c4e1f96ec8 [VMOVD reg4:r1 reg4:r0]
decode c5f22ac0 [VCVTSI2SS reg16:r0 reg16:r1 reg4:r0]
decode32 c4e1f22ac0 [VCVTSI2SS reg16:r0 reg16:r1 reg4:r0]
decode64 c4e1f22ac0 [VCVTSI2SS reg16:r0 reg16:r1 reg8:r0]