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instrs: Add FLD and fix FUCOMIP instructions

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This commit is contained in:
Alexis Engelke
2021-01-10 14:03:43 +01:00
parent c87264ace3
commit d40ee6db66
2 changed files with 12 additions and 1 deletions
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3
instrs.txt
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@@ -1294,6 +1294,7 @@ d9/4m M MEMZ - - - FLDENV
d9/5m M MEM16 - - - FLDCW d9/5m M MEM16 - - - FLDCW
d9/6m M MEMZ - - - FSTENV d9/6m M MEMZ - - - FSTENV
d9/7m M MEM16 - - - FSTCW d9/7m M MEM16 - - - FSTCW
d9/0r M FPU - - - FLD
d9/1r M FPU - - - FXCH d9/1r M FPU - - - FXCH
d9d0 NP - - - - FNOP d9d0 NP - - - - FNOP
d9e0 NP - - - - FCHS d9e0 NP - - - - FCHS
@@ -1401,8 +1402,8 @@ df/6m M FPU - - - FBSTP
df/7m M MEM64 - - - FISTP ENC_SEPSZ df/7m M MEM64 - - - FISTP ENC_SEPSZ
# FSTSW AX # FSTSW AX
dfe0 A GP16 - - - FSTSW dfe0 A GP16 - - - FSTSW
df/5r AM FPU FPU - - FUCOMIP
df/6r AM FPU FPU - - FCOMIP df/6r AM FPU FPU - - FCOMIP
df/7r AM FPU FPU - - FUCOMIP
# #
# Control Flow Enforcement # Control Flow Enforcement
F3.0f01/5m M GP64 - - - RSTORSSP F3.0f01/5m M GP64 - - - RSTORSSP

10
tests/test_decode.c
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@@ -323,6 +323,16 @@ main(int argc, char** argv)
TEST64("\x40\xc5\xf2\x2a\xc0", "UD"); // VEX+REX TEST64("\x40\xc5\xf2\x2a\xc0", "UD"); // VEX+REX
TEST64("\x40\x26\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); // VEX+REX, but REX doesn't precede VEX TEST64("\x40\x26\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); // VEX+REX, but REX doesn't precede VEX
TEST32("\xd9\x00", "fld dword ptr [eax]");
TEST64("\xd9\x00", "fld dword ptr [rax]");
TEST32("\xdd\x00", "fld qword ptr [eax]");
TEST64("\xdd\x00", "fld qword ptr [rax]");
TEST32("\xdb\x28", "fld tbyte ptr [eax]");
TEST64("\xdb\x28", "fld tbyte ptr [rax]");
TEST("\xd9\xc1", "fld st(1)");
TEST("\xdf\xe9", "fucomip st(0), st(1)");
TEST64("\x45\xdf\xe9", "fucomip st(0), st(1)"); // REX.RB are ignored.
TEST32("\xf3\x0f\x7e\x5c\x24\x08", "movq xmm3, qword ptr [esp+0x8]"); TEST32("\xf3\x0f\x7e\x5c\x24\x08", "movq xmm3, qword ptr [esp+0x8]");
TEST64("\xf3\x0f\x7e\x5c\x24\x08", "movq xmm3, qword ptr [rsp+0x8]"); TEST64("\xf3\x0f\x7e\x5c\x24\x08", "movq xmm3, qword ptr [rsp+0x8]");
TEST32("\xc4\xe1\x00\x58\xc1", "vaddps xmm0, xmm7, xmm1"); // MSB in vvvv ignored TEST32("\xc4\xe1\x00\x58\xc1", "vaddps xmm0, xmm7, xmm1"); // MSB in vvvv ignored