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instr: Add weak NOP for PREFETCH register encoding

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Alexis Engelke
2021-01-10 18:54:18 +01:00
parent 9d7b584121
commit cb90c2c54d
1 changed files with 1 additions and 0 deletions
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instrs.txt
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@@ -349,6 +349,7 @@ F2.0f09 NP - - - - WBINVD
0f0d/2m M MEM8 - - - PREFETCHWT1
# All other slots are reserved, AMD maps them to /0
*0f0d/m M MEM8 - - - RESERVED_PREFETCH ONLYAMD
*0f0d/r MR GP GP - - RESERVED_NOP
0f0e NP - - - - FEMMS ONLYAMD
# TODO: actually decode 3DNow! instructions. Given that 3DNow! no longer exists,
# this is unlikely to happen, though.