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encode: Fix [LMS]FENCE encoding

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This commit is contained in:
Alexis Engelke
2023-01-13 11:33:45 +01:00
parent cbbfd9da0e
commit 9f0ddeb44a
3 changed files with 10 additions and 6 deletions
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3
encode-test.inc
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@@ -130,6 +130,9 @@ TEST("", SSE_PEXTRBrri, 0, FE_CH, FE_XMM0, 2);
#endif #endif
TEST("\x66\x0f\xf7\xc1", SSE_MASKMOVDQUrr, 0, FE_XMM0, FE_XMM1); TEST("\x66\x0f\xf7\xc1", SSE_MASKMOVDQUrr, 0, FE_XMM0, FE_XMM1);
TEST("\x67\x66\x0f\xf7\xc1", SSE_MASKMOVDQUrr, FE_ADDR32, FE_XMM0, FE_XMM1); TEST("\x67\x66\x0f\xf7\xc1", SSE_MASKMOVDQUrr, FE_ADDR32, FE_XMM0, FE_XMM1);
TEST("\x0f\xae\xe8", LFENCE, 0);
TEST("\x0f\xae\xf0", MFENCE, 0);
TEST("\x0f\xae\xf8", SFENCE, 0);
// Test FD/TD encodings // Test FD/TD encodings
TEST("\xa0\x00\x00\x00\x00\x00\x00\x00\x00", MOV8ra, 0, FE_AX, 0); TEST("\xa0\x00\x00\x00\x00\x00\x00\x00\x00", MOV8ra, 0, FE_AX, 0);

6
instrs.txt
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@@ -731,9 +731,9 @@ NP.0fae/0m M M - - - FXSAVE+w F=FXSR
NP.0fae/1m M M - - - FXRSTOR+w F=FXSR NP.0fae/1m M M - - - FXRSTOR+w F=FXSR
NP.0fae/2m M Md - - - LDMXCSR F=SSE NP.0fae/2m M Md - - - LDMXCSR F=SSE
NP.0fae/3m M Md - - - STMXCSR F=SSE NP.0fae/3m M Md - - - STMXCSR F=SSE
NP.0fae/5r NP - - - - LFENCE F=SSE2 NP.0faee8+ NP - - - - LFENCE F=SSE2
NP.0fae/6r NP - - - - MFENCE F=SSE2 NP.0faef0+ NP - - - - MFENCE F=SSE2
NP.0fae/7r NP - - - - SFENCE F=SSE NP.0faef8+ NP - - - - SFENCE F=SSE
NP.0fc2 RMI Vps Wps Ib - SSE_CMPPS F=SSE NP.0fc2 RMI Vps Wps Ib - SSE_CMPPS F=SSE
66.0fc2 RMI Vpd Wpd Ib - SSE_CMPPD F=SSE2 66.0fc2 RMI Vpd Wpd Ib - SSE_CMPPD F=SSE2
F3.0fc2 RMI Vss Wss Ib - SSE_CMPSS F=SSE F3.0fc2 RMI Vss Wss Ib - SSE_CMPSS F=SSE

7
parseinstrs.py
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@@ -326,7 +326,7 @@ opcode_regex = re.compile(
r"(?:W(?P<rexw>[01]|IG)\.)?(?:L(?P<vexl>[01]|IG)\.)?))?" + r"(?:W(?P<rexw>[01]|IG)\.)?(?:L(?P<vexl>[01]|IG)\.)?))?" +
r"(?P<escape>0f38|0f3a|0f|)" + r"(?P<escape>0f38|0f3a|0f|)" +
r"(?P<opcode>[0-9a-f]{2})" + r"(?P<opcode>[0-9a-f]{2})" +
r"(?:(?P<extended>\+)|/(?P<modreg>[0-7]|[rm]|[0-7][rm])|(?P<opcext>[c-f][0-9a-f]))?$") r"(?:/(?P<modreg>[0-7]|[rm]|[0-7][rm])|(?P<opcext>[c-f][0-9a-f]))?(?P<extended>\+)?$")
class Opcode(NamedTuple): class Opcode(NamedTuple):
prefix: Union[None, str] # None/NP/66/F2/F3/NFx prefix: Union[None, str] # None/NP/66/F2/F3/NFx
@@ -397,7 +397,7 @@ class Trie:
def _transform_opcode(self, opc): def _transform_opcode(self, opc):
troot = [opc.escape | opc.vex << 2] troot = [opc.escape | opc.vex << 2]
t256 = [opc.opc + i for i in range(8 if opc.extended else 1)] t256 = [opc.opc + i for i in range(8 if opc.extended and not opc.opcext else 1)]
tprefix, t16, t8e, tvex = None, None, None, None tprefix, t16, t8e, tvex = None, None, None, None
if opc.prefix == "NFx": if opc.prefix == "NFx":
tprefix = [0, 1] tprefix = [0, 1]
@@ -405,7 +405,8 @@ class Trie:
tprefix = [["NP", "66", "F3", "F2"].index(opc.prefix)] tprefix = [["NP", "66", "F3", "F2"].index(opc.prefix)]
if opc.opcext: if opc.opcext:
t16 = [((opc.opcext - 0xc0) >> 3) | 8] t16 = [((opc.opcext - 0xc0) >> 3) | 8]
t8e = [opc.opcext & 7] if not opc.extended:
t8e = [opc.opcext & 7]
elif opc.modreg: elif opc.modreg:
# TODO: optimize for /r and /m specifiers to reduce size # TODO: optimize for /r and /m specifiers to reduce size
mod = {"m": [0], "r": [1<<3], "rm": [0, 1<<3]}[opc.modreg[1]] mod = {"m": [0], "r": [1<<3], "rm": [0, 1<<3]}[opc.modreg[1]]