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instrs: Add AVX-IFMI (VPMADD52[LH]UQ)

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Alexis Engelke
2022-11-27 13:37:24 +01:00
parent e411e1327b
commit 64f0ae245e
3 changed files with 14 additions and 0 deletions
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5
decode-test.c
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@@ -652,6 +652,11 @@ main(int argc, char** argv)
TEST("\xc4\xe2\x7a\x72\xc1", "vcvtneps2bf16 xmm0, xmm1"); TEST("\xc4\xe2\x7a\x72\xc1", "vcvtneps2bf16 xmm0, xmm1");
TEST("\xc4\xe2\x7e\x72\xc1", "vcvtneps2bf16 xmm0, ymm1"); TEST("\xc4\xe2\x7e\x72\xc1", "vcvtneps2bf16 xmm0, ymm1");
TEST("\xc4\xe2\xf1\xb4\xc2", "vpmadd52luq xmm0, xmm1, xmm2");
TEST("\xc4\xe2\xf5\xb4\xc2", "vpmadd52luq ymm0, ymm1, ymm2");
TEST("\xc4\xe2\xf1\xb5\xc2", "vpmadd52huq xmm0, xmm1, xmm2");
TEST("\xc4\xe2\xf5\xb5\xc2", "vpmadd52huq ymm0, ymm1, ymm2");
TEST("\xc4\xe2\x71\x92\xc0", "UD"); // Must have memory operand TEST("\xc4\xe2\x71\x92\xc0", "UD"); // Must have memory operand
TEST("\xc4\xe2\x71\x92\x00", "UD"); // Must have SIB byte TEST("\xc4\xe2\x71\x92\x00", "UD"); // Must have SIB byte
TEST("\xc4\xe2\x71\x92\x05\x00\x00\x00\x00", "UD"); // Must have SIB byte TEST("\xc4\xe2\x71\x92\x05\x00\x00\x00\x00", "UD"); // Must have SIB byte

5
encode-test.inc
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@@ -354,6 +354,11 @@ TEST("\xc4\xe2\x7e\xb1\x08", VBCSTNEBF162PS256rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, F
TEST("\xc4\xe2\x7a\x72\xc1", VCVTNEPS2BF16_128rr, 0, FE_XMM0, FE_XMM1); TEST("\xc4\xe2\x7a\x72\xc1", VCVTNEPS2BF16_128rr, 0, FE_XMM0, FE_XMM1);
TEST("\xc4\xe2\x7e\x72\xc1", VCVTNEPS2BF16_256rr, 0, FE_XMM0, FE_XMM1); TEST("\xc4\xe2\x7e\x72\xc1", VCVTNEPS2BF16_256rr, 0, FE_XMM0, FE_XMM1);
TEST("\xc4\xe2\xf1\xb4\xc2", VPMADD52LUQ128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2);
TEST("\xc4\xe2\xf5\xb4\xc2", VPMADD52LUQ256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2);
TEST("\xc4\xe2\xf1\xb5\xc2", VPMADD52HUQ128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2);
TEST("\xc4\xe2\xf5\xb5\xc2", VPMADD52HUQ256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2);
// Test ModRM encoding // Test ModRM encoding
TEST("\x01\x00", ADD32mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX); TEST("\x01\x00", ADD32mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX);
TEST("\x01\x04\x24", ADD32mr, 0, FE_MEM(FE_SP, 0, FE_NOREG, 0), FE_AX); TEST("\x01\x04\x24", ADD32mr, 0, FE_MEM(FE_SP, 0, FE_NOREG, 0), FE_AX);

4
instrs.txt
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@@ -1616,6 +1616,10 @@ VEX.F3.W0.0f38b1/m RM Vx Mw - - VBCSTNEBF162PS F=AVX-NE-CONVERT
# TODO: Vdq is actually half the vector size # TODO: Vdq is actually half the vector size
VEX.F3.W0.0f3872 RM Vdq Wps - - VCVTNEPS2BF16 F=AVX-NE-CONVERT VEX.F3.W0.0f3872 RM Vdq Wps - - VCVTNEPS2BF16 F=AVX-NE-CONVERT
# AVX-IFMA
VEX.66.W1.0f38b4 RVM Vx Hx Wx - VPMADD52LUQ F=AVX-IFMA
VEX.66.W1.0f38b5 RVM Vx Hx Wx - VPMADD52HUQ F=AVX-IFMA
# HRESET # HRESET
#F3.0f3af0c0 IA Ib Rd - - HRESET F=HRESET #F3.0f3af0c0 IA Ib Rd - - HRESET F=HRESET