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decode: Store CL as register operand for shifts

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This commit is contained in:
Alexis Engelke
2020-02-19 16:53:59 +01:00
parent e65086c76c
commit 513a913feb
4 changed files with 24 additions and 18 deletions
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3
decode.c
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@@ -309,6 +309,7 @@ struct InstrDesc
#define DESC_IMM_CONTROL(desc) (((desc)->immediate >> 4) & 0x7) #define DESC_IMM_CONTROL(desc) (((desc)->immediate >> 4) & 0x7)
#define DESC_IMM_IDX(desc) (((desc)->immediate & 3) ^ 3) #define DESC_IMM_IDX(desc) (((desc)->immediate & 3) ^ 3)
#define DESC_IMM_BYTE(desc) (((desc)->immediate >> 7) & 1) #define DESC_IMM_BYTE(desc) (((desc)->immediate >> 7) & 1)
#define DESC_IMPLICIT_VAL(desc) (((desc)->immediate >> 2) & 1)
int int
fd_decode(const uint8_t* buffer, size_t len_sz, int mode_int, uintptr_t address, fd_decode(const uint8_t* buffer, size_t len_sz, int mode_int, uintptr_t address,
@@ -465,7 +466,7 @@ fd_decode(const uint8_t* buffer, size_t len_sz, int mode_int, uintptr_t address,
{ {
FdOp* operand = &instr->operands[DESC_IMPLICIT_IDX(desc)]; FdOp* operand = &instr->operands[DESC_IMPLICIT_IDX(desc)];
operand->type = FD_OT_REG; operand->type = FD_OT_REG;
operand->reg = 0; operand->reg = DESC_IMPLICIT_VAL(desc);
} }
if (DESC_HAS_MODRM(desc)) if (DESC_HAS_MODRM(desc))

32
instrs.txt
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@@ -224,20 +224,20 @@ d1/3 M1 GP IMM8 - - RCR_IMM
d1/4 M1 GP IMM8 - - SHL_IMM d1/4 M1 GP IMM8 - - SHL_IMM
d1/5 M1 GP IMM8 - - SHR_IMM d1/5 M1 GP IMM8 - - SHR_IMM
d1/7 M1 GP IMM8 - - SAR_IMM d1/7 M1 GP IMM8 - - SAR_IMM
d2/0 M GP - - - ROL_CL SIZE_8 d2/0 MC GP GP8 - - ROL_CL SIZE_8
d2/1 M GP - - - ROR_CL SIZE_8 d2/1 MC GP GP8 - - ROR_CL SIZE_8
d2/2 M GP - - - RCL_CL SIZE_8 d2/2 MC GP GP8 - - RCL_CL SIZE_8
d2/3 M GP - - - RCR_CL SIZE_8 d2/3 MC GP GP8 - - RCR_CL SIZE_8
d2/4 M GP - - - SHL_CL SIZE_8 d2/4 MC GP GP8 - - SHL_CL SIZE_8
d2/5 M GP - - - SHR_CL SIZE_8 d2/5 MC GP GP8 - - SHR_CL SIZE_8
d2/7 M GP - - - SAR_CL SIZE_8 d2/7 MC GP GP8 - - SAR_CL SIZE_8
d3/0 M GP - - - ROL_CL d3/0 MC GP GP8 - - ROL_CL
d3/1 M GP - - - ROR_CL d3/1 MC GP GP8 - - ROR_CL
d3/2 M GP - - - RCL_CL d3/2 MC GP GP8 - - RCL_CL
d3/3 M GP - - - RCR_CL d3/3 MC GP GP8 - - RCR_CL
d3/4 M GP - - - SHL_CL d3/4 MC GP GP8 - - SHL_CL
d3/5 M GP - - - SHR_CL d3/5 MC GP GP8 - - SHR_CL
d3/7 M GP - - - SAR_CL d3/7 MC GP GP8 - - SAR_CL
d4 I IMM - - - AAM ONLY32 SIZE_8 IMM_8 d4 I IMM - - - AAM ONLY32 SIZE_8 IMM_8
d5 I IMM - - - AAD ONLY32 SIZE_8 IMM_8 d5 I IMM - - - AAD ONLY32 SIZE_8 IMM_8
#d6 unused #d6 unused
@@ -418,13 +418,13 @@ NP.0f37 NP - - - - GETSEC
0fa2 NP - - - - CPUID 0fa2 NP - - - - CPUID
0fa3 MR GP GP - - BT 0fa3 MR GP GP - - BT
0fa4 MRI GP GP IMM8 - SHLD_IMM IMM_8 0fa4 MRI GP GP IMM8 - SHLD_IMM IMM_8
0fa5 MR GP GP - - SHLD_CL 0fa5 MRC GP GP GP8 - SHLD_CL
0fa8 NP - - - - PUSH_GS DEF64 INSTR_WIDTH 0fa8 NP - - - - PUSH_GS DEF64 INSTR_WIDTH
0fa9 NP - - - - POP_GS DEF64 INSTR_WIDTH 0fa9 NP - - - - POP_GS DEF64 INSTR_WIDTH
0faa NP - - - - RSM 0faa NP - - - - RSM
0fab MR GP GP - - BTS LOCK 0fab MR GP GP - - BTS LOCK
0fac MRI GP GP IMM8 - SHRD_IMM IMM_8 0fac MRI GP GP IMM8 - SHRD_IMM IMM_8
0fad MR GP GP - - SHRD_CL 0fad MRC GP GP GP8 - SHRD_CL
0faf RM GP GP - - IMUL2 0faf RM GP GP - - IMUL2
0fb0 MR GP GP - - CMPXCHG SIZE_8 LOCK 0fb0 MR GP GP - - CMPXCHG SIZE_8 LOCK
0fb1 MR GP GP - - CMPXCHG LOCK 0fb1 MR GP GP - - CMPXCHG LOCK

5
parseinstrs.py
View File

@@ -35,7 +35,8 @@ InstrFlags = bitstruct("InstrFlags", [
"op2_size:2", "op2_size:2",
"op3_size:2", "op3_size:2",
"imm_idx:2", "imm_idx:2",
"imm_size:2", "zeroreg_val:1",
"_unused:1",
"imm_control:3", "imm_control:3",
"imm_byte:1", "imm_byte:1",
"gp_size_8:1", "gp_size_8:1",
@@ -55,11 +56,13 @@ ENCODINGS = {
"M": InstrFlags(modrm_idx=0^3), "M": InstrFlags(modrm_idx=0^3),
"M1": InstrFlags(modrm_idx=0^3, imm_idx=1^3, imm_control=1), "M1": InstrFlags(modrm_idx=0^3, imm_idx=1^3, imm_control=1),
"MI": InstrFlags(modrm_idx=0^3, imm_idx=1^3, imm_control=3), "MI": InstrFlags(modrm_idx=0^3, imm_idx=1^3, imm_control=3),
"MC": InstrFlags(modrm_idx=0^3, zeroreg_idx=1^3, zeroreg_val=1),
"MR": InstrFlags(modrm_idx=0^3, modreg_idx=1^3), "MR": InstrFlags(modrm_idx=0^3, modreg_idx=1^3),
"RM": InstrFlags(modrm_idx=1^3, modreg_idx=0^3), "RM": InstrFlags(modrm_idx=1^3, modreg_idx=0^3),
"RMA": InstrFlags(modrm_idx=1^3, modreg_idx=0^3, zeroreg_idx=2^3), "RMA": InstrFlags(modrm_idx=1^3, modreg_idx=0^3, zeroreg_idx=2^3),
"MRI": InstrFlags(modrm_idx=0^3, modreg_idx=1^3, imm_idx=2^3, imm_control=3), "MRI": InstrFlags(modrm_idx=0^3, modreg_idx=1^3, imm_idx=2^3, imm_control=3),
"RMI": InstrFlags(modrm_idx=1^3, modreg_idx=0^3, imm_idx=2^3, imm_control=3), "RMI": InstrFlags(modrm_idx=1^3, modreg_idx=0^3, imm_idx=2^3, imm_control=3),
"MRC": InstrFlags(modrm_idx=0^3, modreg_idx=1^3, zeroreg_idx=2^3, zeroreg_val=1),
"I": InstrFlags(imm_idx=0^3, imm_control=3), "I": InstrFlags(imm_idx=0^3, imm_control=3),
"IA": InstrFlags(zeroreg_idx=0^3, imm_idx=1^3, imm_control=3), "IA": InstrFlags(zeroreg_idx=0^3, imm_idx=1^3, imm_control=3),
"O": InstrFlags(modreg_idx=0^3), "O": InstrFlags(modreg_idx=0^3),

2
tests/decode-enter.sh
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@@ -7,3 +7,5 @@ decode32 c8000001 [ENTER_4 imm4:0x10000]
decode64 c8000000 [ENTER_8 imm4:0x0] decode64 c8000000 [ENTER_8 imm4:0x0]
decode64 c8000f00 [ENTER_8 imm4:0xf00] decode64 c8000f00 [ENTER_8 imm4:0xf00]
decode64 c8000001 [ENTER_8 imm4:0x10000] decode64 c8000001 [ENTER_8 imm4:0x10000]
decode64 d3e0 [SHL_CL reg4:r0 reg1:r1]
decode64 0fa5d0 [SHLD_CL reg4:r0 reg4:r2 reg1:r1]